1. Technical Field
The present disclosure relates to Serial/Deserializer (SerDes) devices.
2. Background Information
Traditionally, the bus in a computer between the computer's Central Processing Unit (CPU) and the computer's main memory was a parallel bus. As the processing throughput of computers increased, and as demands on memory bandwidth increased, it became increasingly common for the bus between the CPU and memory to be implemented as one or more Serializer/Deserializer (SerDes) links. These SerDes links have tended to be relatively expensive and generally have consumed large amounts of power. SerDes links have therefore generally not been considered suitable for use in mobile devices (such as cellular telephones) where keeping power consumption low is very important. Recently, however, there has been a movement to use SerDes or SerDes-like technologies in low power mobile devices such as cellular telephones. For example, there is a JEDEC (Joint Electron Device Engineering Council) proposed standard under discussion for a SerDes interface. This proposed standard includes power saving features to make the proposed SerDes interface more suitable for low power mobile devices. In addition to the SerDes interface in the proposed JEDEC standard, there are numerous other known SerDes designs. These standards and known designs have included numerous features and methods for reducing power consumption.
A first example of such a power saving feature involves placing the SerDes interface in a low-power mode when the interface is not being actively accessed by the processor. Because of the inherent random-access use of memory by a typical CPU, however, the memory must essentially be available to the processor most of the time (with the exception of sleep mode operation). As a result, this first example of power saving is only minimally effective in reducing power consumption. A second example of a power saving feature involves cutting power to and disabling the PLL (Phase-Locked Loop) and (CDR) Clock and Data Recovery circuitry of the SerDes. Each side of a SerDes link includes a PLL and CDR. This circuitry may consume a lot of power. It is possible to turn these circuits off to reduce power consumption when the interface is not active. Unfortunately, there is an amount of time required to turn these circuits back on (settling and lock time of the PLL) and have them functional again. If these circuits are in their off states when the processor needs access to the memory, there will be a delay until the memory can be accessed via the SerDes links and that delay effectively stalls the processor. This is undesirable. A third example of a power saving feature is set forth in Published U.S. patent application US2006/0115316. In this example the signal swing of the SerDes transmitter is made only as large as it has to be to prevent transmission errors. However, for mobile applications there remains a need for more power savings, and in both the first and second examples principal power savings is achieved by making the SerDes interface unusable and inactive for part of the time such that processor use of the interface is complicated and partially compromised.